Digital to analog convertor

ABSTRACT

A method and circuit are provided for converting a digital signal to an analog signal in the form of a pulse width modulated (PWM) pulse ( 20 ). The PWM pulse is generated during an output cycle of a pulse generator to form a pulsetrain output of pulses at a fixed frequency whose widths are determined by dynamically changing digital input data. The method includes the steps of dividing the digital data signal into most significant bit (MSB) and least significant bit (LSB) portions. A PWM pulse is initiated at the beginning of an output cycle and continues while the MSB portion counts down in a counter ( 24 ). At the same time, the LSB portion of the digital data signal is converted to a precise phase delay signal which is a subcycle of an oscillator controlling the counter. This phase delay signal is generated after the termination of the MSB count, and halts the high period of the PWM pulse during the output cycle. When the output cycle ends, the process is repeated with the next digital signal.

This application is a 321 of PCT/US02/15191 filed on May 13, 2002 whichclaims benefit of the provisional application 60/290,919 filed on May14,2001.

BACKGROUND OF THE INVENTION

Digital to analog conversion circuits (DAC) with pulse-width modulated(PWM) outputs are common, but have not used subcycle precision timers togenerate pulse width variations, and generally require extensive outputfiltering. As a result, output resolutions are limited to the highestfrequency digital clock rates and counter speeds possible in a giventechnology. Where the technology permits high-speed docks, high powerconsumption and excessive heat generation result.

A commonly used method for generating PWM output is through the use of astandard DAC for analog generation. The resulting analog signal is thenconverted to PWM using analog modulation circuitry. This techniquesuffers from a lack of accuracy and controllability, and requiresadditional circuitry.

Delta-Sigma DAC circuits and over-sampling techniques use filtering toreduce undesired output noise. Delta-Sigma DACs use low-resolutionhigh-speed DACs to create high-resolution lower speed outputs usinginterpolation techniques. By example, a 4 MHZ over-sampling rate mightbe used for 44 KHz audio. Sample values would be digitally interpolatedprior to using a 1-bit DAC. The over-sampled pulse-position signal wouldbe low-pass filtered, leaving only the desired output waveform. Suchfiltering processes take substantial amounts of time and requireextensive additional circuitry. Phase distortion is introduced by thesetechniques, thus further deteriorating the quality of the outputsignals.

BRIEF SUMMARY OF THE INVENTION

A method and circuit are provided for converting a digital signal to ananalog signal in the form of a pulse width modulated (PWM) pulse. ThePWM pulse is generated during an output cycle of a pulse generator toform a pulsetrain output of pulses at a fixed frequency whose widths aredetermined by dynamically changing digital input data. The methodincludes the steps of dividing the digital data signal into mostsignificant bit (MSB) and least significant bit (LSB) portions. A PWMpulse is initiated at the beginning of an output cycle and continueswhile the MSB portion counts down in a counter. At the same time, theLSB portion of the digital data signal is converted to a precise phasedelay signal which is a subcycle of an oscillator controlling thecounter. This phase delay signal is generated after the termination ofthe MSB count, and halts the high period of the PWM pulse during theoutput cycle. When the output cycle ends, the process is repeated withthe next digital signal.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a block schematic diagram of the preferred embodiment of theinvention, a high-speed DAC circuit utilizing PWM technology.

FIG. 2 is a block schematic diagram illustrating a high-speed rippleoscillator for high-resolution intervals which is used in the embodimentof FIG. 1.

FIG. 2A is a wave form diagram of the subcycle phase delay pulsesgenerated by the ripple oscillator of FIG. 2.

FIG. 3 is a wave form diagram showing the timing relationship betweenthe output cycle period, the PWM pulse, and the subcycle phase delaypulses.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

This invention is a high precision DAC circuit that converts digitaldata streams to varying pulse widths or analog outputs at high datarates. Digital data stream numbers representing digital pulse widthtimes are converted to subcycle precision pulse width modulated signals.This is accomplished by utilizing a high-speed oscillator to generate acontinuous square wave. The oscillator has taps for selecting multiplephases of the square wave, facilitating subcycle timing. Incomingdigital numbers are split into two sections, the least significantportion (LSB) is used to select a subcycle phase and the mostsignificant portion (MSB) is used for a counter. The size of the leastsignificant portion is determined by the number of taps in theoscillator, while the remaining most significant value is used forcounters. The longest portion of the pulse width is timed through theuse of digital counters using the MSB portion of the split number. Thesmaller portion of the pulse width time is too short to determine usingcounters. This subcycle time is determined using the least significantsection of the number to choose a phase from the tapped oscillatoroutputs through a selector. Each selected phase has a different timedelay with respect to the rising edge of the oscillator's square waveoutput, increasing with each delay element in the oscillator. Largerselection numbers choose larger subcycle delay times. This subcyclesignal in conjunction with the counter time is then used to control thewidth of an output pulse. As a result, the output PWM pulse widths havethe timing precision of a single delay element, and have a dynamic rangefrom extremely short subcycle intervals to extremely long multi-cycleintervals.

For analog output requirements, the PWM output signals can be timeaveraged. The resultant time averaged output analog voltage or currentfollows the magnitude of the digital input stream. Additional circuitrycan output the PWM signals as true analog voltages or currents.

The major advantages of this circuit are that it provides much higherresolution PWM control with lower noise interference, and at lower powerwith less heat generation. Through inherent filtering by the resistive,capacitive, and inductive loading of external circuitry, the high-speedoutput rate of this invention reduces the need for output filters, ofteneliminating them entirely.

Digital Amplifiers can be implemented more effectively through the useof the circuit since the unfiltered PWM output of this invention candrive digital high frequency power output stages directly.

Headphones, amplifiers, and other analog devices can be driven directlyfrom the digital PWM outputs due to the inherent low-pass filtering ofthe devices. Due to the circuit's high resolution and high-speedoperation, this invention is sufficiently accurate to output commercialquality analog audio, video and radio signals. The invention's smallerand simpler circuitry results in markedly less phase distortion withmore accurate reconstructions of the original digitized signals.

This invention is well suited for use in Delta-Sigma over-samplingcircuitry for higher resolution conversions, yielding considerablyhigher resolutions than are achievable using existing technology. As instandard Delta-Sigma conversions, this is accomplished at the sacrificeof conversion time and is principally suited for low frequencyoperations.

Referring to FIG. 1, a high-speed digital to analog circuit (DAC) 10includes a ripple oscillator 12, a latch A 14 and latch B 16. Latch B 16is coupled to a cycle time counter 18. The “enable set” input of a pulsegenerator 20 is coupled to the output of cycle time counter 18. Thepulse generator 20 is a PWM pulse generator whose “pulsetrain output”consists of pulses of varying width but having a fixed frequency. Thewidth of each pulse in the “pulsetrain output” is determined by thenumerical value of the digital input signals loaded into latch A. LatchA 14 is periodically loaded with binary data which changes the outputpulse width durations within repeating sample cycle durations at the“pulsetrain output” of pulse generator 20.

Latch A 14 loads a pulse width count signal when it is clocked by asignal from synchronization circuit 22. Latch A 14 has two outputs. Thehigh-bits output contains a signal representative of the mostsignificant bits (MSB) of the input digital signal. The low-bits outputcontains the least significant bits (LSB) of the digital signal heldwithin the latch. For illustration purposes, it will be assumed for thisexample that the “pulse width count” signal is a digital audio signalwhich is a 16-bit signal reoccurring at a 44 KHz rate. The “high-bits”output of latch A 14 is coupled to a pulse time counter 24. The outputof the counter 24 is connected to the “enable” pin of a polarity window26. In turn, the output of the polarity window 26 is coupled to the“enable clear” input of the pulse generator 20. The low-bits output oflatch A 14 is connected to the selection input of a (MUX) 28. The MUX 28contains inputs D₀ through D_(N) which represent delays of differingphase of the pulses generated by the ripple oscillator 12. The output ofthe MUX 28 is a selected phase of the ripple oscillator selected in theMUX 28 by the low-bits line less the highest of the LSB number bits. Thehighest bit of the LSB output on the low-bits line is coupled to latch C30. The output of latch C 30 is coupled to an input of XOR gate 32 alongwith the selected phase output of the MUX 28. This same output is alsocoupled as the “even odd” input of the polarity window circuit 26. Theoutput of the XOR gate 32 is coupled to the pulse generator 20 on its“clear” input. Thus, the high portion of the PWM pulse of the pulsegenerator 20 is enabled at the beginning of an output cycle andcontinues until the end of the MSB portion at which time the “clear”function is enabled by the polarity window 26. The PWM pulse continues,however, until cleared by a signal from XOR gate 32 which represents thephase delay within ripple oscillator 12 caused by the LSB portionselection in MUX 28.

Referring to FIG. 1, one of the phase delay lines D₀ through D_(N) ofthe ripple oscillator 12 is selected by the multiplexor 28 for thesubcycle timing precision required to generate a pulse width modulatedpulse that precisely matches the binary data which is periodicallyloaded into latch A 14. The width of this pulse varies within a constantoverall pulse width cycle time which sets the duration for each outputsample at the pulsetrain output of the pulse generator 20. Latch B 16 isloaded with a signal representing a constant overall pulse width cycletime. The ripple oscillator 12 generates a constant frequency squarewave by feeding a negative signal back to its input D₀ from a pointalong a series of delay elements thus maintaining oscillation (refer toFIG. 2). Tap signals from each delay element are at different phasetimings of this oscillator square wave with respect to the reference tapD₀ (refer to FIG. 3).

Referring again to FIG. 1, initialization of the circuit requires aone-time loading of latch B 16 to set a repeating cycle time. For theexample chosen, this may be set for a repetition rate of 880 KHz. Inorder to maintain CD quality audio, latch A 14 must be loadedperiodically with 16-bit data at a 44 KHz rate. Within the cycle time oflatch B 16, the pulse generator 20 generates a pulse having a durationthat is defined by the digital data value loaded into latch A 14. In theexample chosen, twenty cycle times occur between each introduction ofnew data into latch A 14. Sample cycles begin when the cycle timecounter counts down to zero, thus generating a “cycle done” pulse thatenables a “reference phase” signal from the ripple oscillator 12 to load16-bit data into the pulse time counter 24 and the cycle time count fromlatch B 16 into the cycle time counter 18. The “cycle done” pulse alsoenables the pulse generator 20 so that its output is set “high” at thebeginning of the next cycle. During the cycle interval, the “referencephase” signal clocks down both pulse time counter 24 and cycle timecounter 18. The pulse time counter 24 reaches zero first due to asmaller count value than that of the cycle time counter 18. When thepulse time counter 24 reaches zero, a “pulse done” signal is generated.This signal, which is coupled to the “enable” input of the polaritywindow circuit 26, allows the output of the pulse generator 20 to be setlow on the rising edge of the output pulse from XOR gate 32 thus endingthe “high” portion of the PWM. The remainder of the output cycle timecontinues to be counted by the cycle time counter 18 at which time the“cycle done” pulse begins a new sample cycle which is repeatedgenerating the same PWM pulse until another value is stored in latch A14 that changes the pulse width. Thus, the combination of the high-bitand low-bit portions of the 16-bit data periodically loaded into latch A14 controls in an extremely precise way the variable width pulsesgenerated by the pulse generator 20 within the sample cycle timeinterval as defined by the data in latch B 16 and the cycle time counter18.

FIG. 3 illustrates the precision of the PWM output pulse provided by thepulse generator 20. By selecting a delay line D₀ through D_(N) of theripple oscillator output lines, a “subcycle” pulse is generated whichrepresents a fraction of a complete cycle of the ripple oscillator 12.This is shown with reference to the “Magnified Oscillator Cycle TimingDiagram” of FIG. 3. It can be seen in the selected case that theselected phase delay has, in effect, phase shifted the output of theoscillator from the dashed line on the left side of the diagram to thedashed line toward the center of the diagram which amounts to a fractionof a complete oscillator cycle. By selecting one of the phase delayedlines D₀ through D_(N), the oscillator's output is broken down intosubcycles which may be selected to precisely control the timing of thePWM output at generator 20 by a value representing the least significantbits of the data loaded in latch A 14.

Because the oscillator cycle can be either high or low when the phaseselection is made, circuitry is required to choose the polarity of theselected phase and provide a rising edge at the precise time required toend the pulse “high” time in the pulse generator 20. The rippleoscillator 12 has delay elements that cycle, high then low, to generatea full square wave. The oscillator has a rising edge at each of thedelay elements only during the first half of the square wave. Since allof the delay elements output falling edges during the second half of theoscillator square wave cycle, inversion of the selected phase changesthese phases to rising edges. The XOR gate 32 provides a means forselectively inverting the signal. The “highest low bit” binary signal isthe next higher bit above the phase selection number and is used tocause signal inversion in the XOR gate 32 for timing selections modeduring the second half of the square wave. Latch C 30 insures that thehighest low bit inversion control is only changed at the beginning of anew cycle to prevent data changes in latch A 14 from affecting the XORgate 32 at an inappropriate time. Since latch A 14 is loadedasynchronously with respect to the oscillator's “reference phase”signal, synchronizing circuitry in sync circuit 22 for loading latch A14 is necessary to prevent metastable conditions when the pulse timecounter 24 is loaded. Since latch B 16 is loaded only once,synchronizing circuitry is unnecessary as any metastable condition thatcould exist is corrected on the next loading of the cycle time counter18.

Additional and Alternative Embodiments

To achieve even higher resolution and reduced noise, this invention mayreplace DAC circuits within present Delta-Sigma DAC technology. Whenincorporated into Delta-Sigma DAC circuits, this invention produces ntimes less high frequency noise power compared to the currentDelta-Sigma interpolating DACs, where n is the timer resolution of thePulse width time interval measuring circuit divided by the Delta-SigmaConverter's over-sampling time period. To illustrate this point, a 1 MHZDelta-Sigma Converter might over-sample audio by 20 times the audiosampling rate. A typical Delta-Sigma quantizer uses a 1-bit clocked DAC,adding large amounts of high frequency noise power to the incomingdigitized analog signal. A state-of-the-art Delta Sigma Converter usinga 1 bit DAC operating at 1 MHZ thus has a one microsecond pulse edgeplacement inaccuracy. The resultant high frequency noise must befiltered out for an acceptable output. Typically, this is accomplishedby using a 101-tap digital interpolative FIR filter and an analog lowpass filter at the cost of additional long-latency, extensive circuitry.When incorporated into an existing Delta-Sigma circuit, this inventionwould produce only {fraction (1/50,000)}^(th) of the correspondingDelta-Sigma's noise power when using 20-picosecond resolution sub cycledelay taps, and less noise would result from even smaller resolutionintervals. Thus, this invention's noise factor is so low that little ifany digital filtering is needed. The magnitude of the output analog highfrequency noise is also lower and is mostly at a single frequency whichsimplifies the analog output filter requirements.

Various delay element tuning methods may be employed for high accuracyapplications. Laser trimming, floating gate settable resisters, voltagevariable capacitors, and other methods may be used to adjust individualdelay elements for improved linearity. These controlled delay techniquescan also be combined with analog delay techniques, such as digitallycontrolled analog delay cells.

Delay elements may be synchronized or calibrated to a reference clock,improving the timing repeatability of the DAC oscillator. Delay elementsmay be “current starved” to slow them down as needed. Delay lines may betuned for synchronization by methods such as varying intrinsiccapacitance using voltage-controlled capacitors, or by changinginductance by the use of transformers with DC bias control.

Very precise timing resolutions are achievable by the use of fast delaytechnologies, such as wire delay lines and resonant cavities. Timingresolutions approaching 100 femtoseconds and shorter can be achievedusing such technologies.

The preferred embodiment's precision PWM provides resolutions adequatefor most applications. Greater dynamic ranges may be achieved byseparately controlling the power source for the PWM output stage,thereby changing the output voltages or currents in conjunction withpulse width variations. A second DAC or other control circuit may beused to control voltage levels on the final output stage of the PWM.Floating point numbers may be used for digitally represented analogdata. For example, a 32-bit floating-point number might use a 24-bitmantissa to directly control the DAC invention described above, whilethe 8 bit exponent can control the output levels exponentially. Thesemethods result in outputs that are controllable in billions of steps.Additionally, this invention is not limited to linear time delays,opening the potential for logarithmic or other numerical progressions.

A multitude of output circuit configurations are possible for differentapplications, some stated here:

-   -   1. Transistor pull-up or pull-down only    -   2. Totem-pole pull-up and pull-down    -   3. Tri-voltage output with mid-voltage off state    -   4. Tri-state pull-up and pull-down with off condition    -   5. Full bridge bi-directional drive with dual outputs    -   6. True analog with sample-hold outputs    -   7. True analog with sample-hold complimentary dual outputs.

External power transistors may be driven directly from the PWM outputs.Feedback from final output stages may be used to adjust the invention'soutput signals for optimum performance.

An alternate configuration for this invention is a high-precisionshort-interval programmable delay timer. In this version, a memory arrayis given a list of numbers of sequential delays. After each pulse delay,the output signal is alternately set or reset, the memory pointer isincremented to point to the next data, and the oscillator is cleared tobegin another precision timing cycle. When the last memory entry hasbeen reached, the memory pointer is reset to point to the beginning ofthe list, and for once-only applications the oscillator is stopped. Thisconfiguration generates precision-width single and repetitive complexpulse sequences, and continuous clock outputs with stable precisionpulse widths. This aspect of the invention facilitates high-accuracyvariable duty cycle clock signal generation with precise frequencycontrol.

It should be understood from the foregoing that this inventioncontemplates that alternative implementations of its pulse generatingcircuitry can be used to selectively center the pulse widths around anyreference location within the pulse repetition timing count to reduceharmonic distortion.

While various embodiments of the present invention have been describedabove, it should be understood that they have been presented by way ofexample, and not limitation. Thus, the breadth and scope of the presentinvention should not be limited by any of the above-described exemplaryembodiments, but should be defined only in accordance with the followingclaims and their equivalents. It will be understood by those skilled inthe art that various changes in form and detail may be made thereinwithout departing from the spirit and scope of the invention.

The terms and expressions which have been employed in the foregoingspecification are used therein as terms of description and not oflimitation, and there is no intention, in the use of such terms andexpressions, of excluding equivalents of the features shown anddescribed or portions thereof, it being recognized that the scope of theinvention is defined and limited only by the claims which follow.

1. A method for converting a digital signal to an analog signal whereinsaid analog signal is in the form of a pulse width modulated (PWM) pulsehaving an output cycle, comprising the steps of: a) dividing saiddigital signal into most significant bit (MSB) and least significant bit(LSB) portions; b) initiating a PWM pulse at the beginning of said MSBportion during said output cycle; c) converting said LSB portion to asubcycle phase delay signal; and d) terminating said PWM pulse with saidsubcycle phase delay signal during said output cycle and after theconclusion of said MSB portion.
 2. The method of claim 1 wherein step(c) is performed by shifting a phase of an oscillator by an amount lessthan a complete cycle of said oscillator.
 3. A digital to analogconvertor (DAC) circuit comprising: a) an input network for receiving adigital data signal and for dividing said digital data signal into amost significant bit (MSB) portion and a least significant bit (LSB)portion; b) a pulse width modulator (PWM) circuit for generating pulsesof varying length within a fixed output cycle; c) a pulse counternetwork for enabling said PWM circuit to begin generating a PWM pulse atthe beginning of said MSB portion of said digital pulse signal; d) aphase delay network responsive to said LSB portion for generating asubcycle pulse; and e) logic means coupling said subcycle pulse to saidPWM circuit after the termination of said MSB portion to determine thewidth of said PWM pulse generated by said PWM circuit.
 4. The DACcircuit of claim 3 wherein said phase delay network comprises a rippleoscillator coupled to a multiplexor said multiplexor having an LSB inputfor selecting a delay phase of said ripple oscillator in response to thevalue of said LSB portion.
 5. The DAC circuit of claim 4 wherein saidlogic means comprises polarity selection means for correcting thepolarity of a selected phase of said ripple oscillator.